As is well known in the art of integrated circuit manufacturing, active electrical structures such as transistors can be built upon crystalline substrates, typically of silicon, to form useful circuits. A typical integrated circuit contains many such electrical structures that are platted or “laid out” upon an area in the top of the substrate. However, because such crystalline substrates are often semiconductive, and hence can carry some degree of current, care must be taken to make sure that a given electrical structure does not electrically interfere with other adjacent electrical structures. To prevent the leakage of current between such electrical structures, the art has traditionally placed isolation structures between the active areas of the substrate which carry the electrical structures.
Many prior art isolation techniques are known. One such technique, illustrated in FIG. 1, is the formation of LOCOS (“LOCal Oxidation of Silicon”) islands 12, which are used to isolate two active regions 14 in a substrate 10. As is well known, LOCOS islands 12 are formed by masking the active regions 14 and oxidizing the silicon substrate to form the silicon dioxide (oxide) LOCOS islands 12. Thereafter, electrical structures, such as transistors 16 (which include a gate 18, source 20, and drain 22) can be fabricated in the active regions 14. The LOCOS islands 12, if properly fabricated, will be wide enough (w) to prevent lateral leakage through the substrate (e.g., from source 20a to drain 22b), and further will be thick enough (t) to prevent voltages from any overlying conductors (not shown) from electrically biasing the underlying substrate in a manner that would further promote such lateral leakage.
Another more recent technique, illustrated in FIG. 2, is the formation of trench isolation structures. Generally, trench isolation structures are formed by masking the active regions 34 and etching a trench 32 into the silicon substrate 30. This trench 32 can then be filled, usually by depositing an oxide or other dielectric onto the etched surface, and etching or polishing the oxide so that it is substantially flush with the surface of the substrate 30 to form a dielectric plug 35. Thereafter, and as with the LOCOS process, electrical structures, such as transistors 36, can be formed in the active regions. The trench isolation structures so formed thus prevent lateral leakage between the electrical structures, as in the LOCOS process.
Many modifications of these prior art techniques exist. For example, to provide further lateral leakage protection, it is known and sometimes desirable to dope the substrate beneath the isolation structure to make it more difficult for lateral leakage currents to flow. For example, if the substrate below the isolation structure is p-type (i.e., rich not in negatively charged electrons but rich in positively charged holes, e.g., by doping with Boron), it may be beneficial to ion implant or diffuse extra p-type dopants (e.g., Boron) into the substrate before formation of the dielectrics that form the isolation structures. The presence of these extra dopants can make it more difficult for lateral currents to flow, and also make it more difficult for any overlying voltages to electrically influence the substrate to inadvertently promote such leakage. The approximate location of such extra dopants, if present, is shown in FIGS. 1 and 2 as element 40. Examples of these prior art techniques, and their various modifications, can be found in the following U.S. patents, which are hereby incorporated by reference: U.S. Pat. Nos. 6,265,282; 6,261,922; 5,895,253; 5,945,724; 6,110,798; 5,953,621; 5,903,026; 5,777,365; 6,238,999; 5,888,881; 5,492,853; 6,274,498; 6,271,153; 6,051,480; 6,322,634; 5,763,932; 6,323,104; 6,165,853; 5,640,034; 6,177,333; 5,977,579; 6,107,157; 6,271,561; 6,340,624; 6,300,219.
Prior art isolation techniques, while suitable for many applications, can have certain drawbacks. Some techniques involve many separate processing steps, which are expensive and/or difficult to manufacture. Other techniques may not provide suitable isolation, either because the isolation structures are too thin (allowing excessive lateral leakage due to parasitic capacitance), or are too susceptible to overlying voltages that, as noted, can assist in promoting lateral leakage. Such problems are further exacerbated when one considers that the integrated circuit industry constantly strives to make smaller (and hence more cost-effective) circuits which are more closely packed together. Without reduction in the voltages used to run the circuits, the shrinking of the geometries of the structures on the integrated circuit chips will increase leakage currents as the thickness or width of the isolation dielectrics also shrinks. Accordingly, an improved isolation structure is desired—one that is simple to manufacture, uses well-known and well-established processing techniques, and which will adequately minimize leakage throughout the substrate even for very small and dense geometries.